As illustrated in FIG. 14, in a conventional liquid crystal display using a TFT as a switching element, on a glass substrate 101 are placed a gate electrode 102 formed through the same process, gate wiring (not shown) connected to the gate electrode 102 and a source signal input terminal 103.
Moreover, a gate insulation film 105 is formed on the entire surface of the glass substrate 101, except for a terminal section contact hole 104 formed on the source signal input terminal 103. On the gate electrode 102 are placed, through a gate insulation film 105, an amorphous silicon semiconductor layer (hereinafter, referred to as a-Si layer) 106 and an amorphous silicon semiconductor layer (hereinafter referred to as n+ a-Si layer) 107. The n+ a-Si layer 107, which is an amorphous silicon semiconductor layer to which an impurity is added, is an ohmic contact layer that is provided so as to ohmic-connect the a-Si layer 106 to a source electrode and a drain electrode, which will be described later.
A source electrode 108 and a drain electrode 109 are placed on the a-Si layer 106 and n+ a-Si layer 107, and a source wire 110 is formed integrally with the source electrode 108 through the same process.
A TFT 111 is constituted by the gate electrode 102, a-Si layer 106, n+a-Si layer 107, source electrode 108, and drain electrode 109, etc., arranged as described above.
Moreover, a protective film 113 and a resin layer 114, which are used for protecting one portion of the source wire 110 and the TFT 111, are formed except for the terminal section contact hole 104 and a display section contact hole 112 formed on the drain electrode 109.
Moreover, the connection electrode 115 is joined to the source signal input terminal 103 so that the source wire 110 and the source signal input terminal 103 are connected to each other through the terminal contact hole 104. Moreover, the display electrode layer 116 and the drain electrode 109 are connected through the display contact hole 112.
The above-mentioned conventional liquid crystal display is manufactured through the following processes (1) to (8):
(1) First, a metal thin film, composed of titanium (Ti), aluminum (Al), or chromium (Cr), etc., is formed on a washed glass substrate 101 by sputtering, etc. Then, a photolithographic technique, which carries out etching by using a mask that is formed by applying photoresist to the metal thin film and exposing and developing it, is used to simultaneously form the gate electrode 102, the gate wire connected to the gate electrode 102 and the source signal input terminal 103.
(2) SiNx, which forms a gate insulation film 105, is formed thereon by using a mixed gas of SiH4/NH3/N2 through a P-CVD method.
(3) an a-Si film is formed on the gate insulation film 105 by using SiH4/H2.gas through a P-CVD method. In the same manner, an n+a-Si film is formed by using SiH4/H2.gas with mixed PH3 through a P-CVD method. Thereafter, the a-Si layer 106 and the n+a-Si layer 107 are patterned through a photolithography technique, etc.
(4) Moreover, a multi-layer structure metal thin-film, such as an Al/Ti thin-film, is formed, and this metal thin film is patterned through a photolithography technique, etc.
so that a source electrode 108, a drain electrode 109 and a source wire 110 are formed.
(5) Next, SiNx is deposited by a P-CVD method using a mixed gas of SiH4/NH3/N2 to form a protective film 113.
(6) On the protective film 113, a resin layer 114, which serves as a second protective film, is patterned and formed through a photolithography method, etc., and is subjected to a heating process, etc. to cure the resin. In this state, terminal section contact holes 104 and display section contact holes 112 are formed in the resin layer 114.
(7) Next, in the terminal section contact hole 104, the gate insulation film 105 and the protective film 113 are simultaneously etched and removed by using the source wire 110 and the resin layer 114 as masks. Here, with respect to the display section contact hole 112 formed in the process (6), since the drain electrode 109 serves as an etching stopper, the gate insulation film 105 beneath it is allowed to remain.
(8) The connection electrode 115 and the display electrode 116 are formed.
Moreover, as illustrated in FIG. 15(a) and FIG. 15(b), in another liquid crystal display, on an insulation substrate 201 made of glass, etc., a gate wire 202 on which a gate signal input terminal 202a and a gate electrode 202b are integrally formed, a support capacity wire 204, a support capacity electrode 204b and support capacity signal input terminal 204a connected to the support capacity wire 204 are formed.
Then, on top of these layers, through a gate insulation film 207, are formed an a-Si layer 208a made of an amorphous silicon semiconductor layer, and an n+a-Si layer 208b that is an amorphous silicon semiconductor layer to which impurities such as phosphor (P) are added so as to realize ohmic connections between the a-Si layer 208a and a source electrode 209b as well as a drain electrode 210.
Next, after a multi-layer structure film, such as an Al/Ti film, not shown, has been deposited on the a-Si layer 208a and n+a-Si layer 208b that are the semiconductors, a source electrode 209b, a drain electrode 210 and a source wire 209 that serves as bus wiring for them are formed. Moreover, a TFT 211 is formed by the source wire 209, a source electrode 209b and a source signal input terminal 209c that are integral with the source wire 209 and a drain electrode 210.
Next, an overcoat layer 212, made of an insulation film such as SiN, for protecting the source wire 209 and TFT 211, and a resin insulation film 213 made of an insulation photosensitive acrylic resin, etc. are successively laminated so that an overcoat layer having a two-layer structure is formed.
Next, the resin insulation film 213, made of a photosensitive acrylic resin, etc., is exposed in an exposing process by using a predetermined mask, and then subjected to a developing process so that a contact hole 215 is formed in the resin insulation film 213. Simultaneously with this process, the resin insulation film 213 over the source signal input terminal 209c, the gate signal input terminal 202a and support capacitor signal input terminal 204a is removed therefrom.
By using the resin insulation film 213 thus patterned as a mask for an etching process, the overcoat layer 212 located at the bottom of the contact hole 215, and the overcoat layer 212 covering the source signal input terminal 209c, the gate signal input terminal 202a and the supplementary capacitance signal input terminal 204a are simultaneously removed.
Successively, by using the resin insulation film 213 patterned as described above as a mask for an etching process, the gate insulation film 207 covering the gate signal input terminal 202a and the supplementary capacitance signal input terminal 204a is removed therefrom.
Next, a pixel display electrode 214, which is used for applying a voltage to liquid crystal formed over the surface of the resin insulation film 213 including the inside of the contact hole 215 formed in the resin insulation film 213, is formed so that the drain electrode 210 on the base section of the contact hole 215 is electrically connected.
However, the above-mentioned manufacturing method for the conventional liquid crystal display has raised the following problems.
In the liquid crystal display having the arrangement shown in FIG. 14, upon simultaneously etching the gate insulation film 105 and the protective film 113 in the above-mentioned process (7), since the source wire 110 serving as the mask is not etched at all, the gate insulation film 105, placed beneath the source wire 110, is selectively etched quickly. This results in a state in which the gate insulation film 105 comes under the source wire 110 (a reversely-tapered shape), and when the connection electrode 115 is formed in the process (8), a step discontinuity section 117 of the connection electrode 115, shown in FIG. 6, tends to be formed. Such a step discontinuity section 117 raises a problem of disconnection between the source signal input terminal 103 and the source wire 110.
Moreover, in the manufacturing method of the liquid crystal display shown in FIG. 15(a) and FIG. 15(b), with respect to the etching rate, the following relationship is given between the resin insulation film 213 and the overcoat layer 212: (etching rate of the resin insulation film 213)<(etching rate of the overcoat layer 212). Moreover, in the case when the etching rate of the drain electrode 210 is not more than 1/10 of that of the overcoat layer 212, while the gate insulation film 207 corresponding to portions of the gate signal input terminal 202a and the supplementary capacitance signal input terminal 204a is being etched, the etching process inside the contact hole 215 stops progressing downward, while it starts proceeding sideways, with the result that the etched portion of the overcoat layer 212 reaches the rear face of the resin insulation film 213, forming a reversely-tapered shape 217.
Consequently, in this state, a step discontinuity occurs in the pixel display electrode 214 that is formed in a succeeding process, resulting in failure in providing electrical connections in the pixel display electrode 214.